Escalating demands for high density and performance associated with ultra large scale integration require semiconductor devices with design features of 0.25 microns and under, e.g. 0.18 microns, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor technology for isolating active regions.
Conventional semiconductor devices comprise a substrate having various electrically isolated regions, called active regions, in which individual circuit components are formed. The active region typically includes source/drain regions of a transistor formed in the semiconductor substrate or epitaxial layer, spaced apart by a channel region. A gate electrode for switching the transistor is formed on the channel with a gate oxide layer therebetween. The quality and thickness of the gate oxide are crucial to performance and device reliability.
The electrical isolation of active regions is typically accomplished by defining field regions bounding the active regions, defined by a source/drain mask applied to a barrier nitride layer deposited over the semiconductor substrate, typically doped monocrystalline silicon or an epitaxial layer formed thereon. An isolating field oxide regions is typically formed by thermal oxidation of semiconductor substrate.
One type of isolation is known as Local Oxidation Of Silicon (LOCOS), in which the entirety of the field oxide is formed by heating the substrate with the field regions exposed to an oxidizing gas, such as oxygen or water vapor. LOCOS methodology, however, disadvantageously results in the formation of a field oxide region having tapering edges, because the oxidizing species for forming the field oxide diffuses horizontally after penetrating the substrate. This tapering end portion resembles and, therefore, is commonly referred to as, a "bird's beak."
LOCOS methodology is thus subject to several inherent problems. For example, while the horizontal extent of the bird's beak can be loosely controlled by the stress induced in the masking layers adjacent to the field, this same stress can cause strain defects in the active areas including point defects, dislocations, stacking faults, as well as catastrophic failures such as delamination, particle generation, etc. Moreover, aggressive scaling of gate electrode dimension into the deep submicron regime, such as less than about 0.25 microns, requires tighter source/drain region to source/drain region spacing, which is adversely affected by the bird's beak attendant upon LOCOS methodology.
Another type of isolation is known as shallow trench isolation (STI). This form of isolation is typically accomplished by etching a trench in the substrate, conducting a thermal oxidation step to grow an oxide liner on the trench walls to control the silicon-silicon dioxide interface quality, and filling the lined trench with an insulating material, such as silicon dioxide derived from tetraethyl orthosilicate (TEOS). The surface is then planarized, as by chemical-mechanical polishing (CMP), to complete the trench isolation structure. A typical trench isolation structure thus comprises an internal surface with side surfaces extending into the substrate (or epitaxial layer) with edges at the main surface of the substrate and at the bottom of the trench.
A difficulty with trench isolation is that the sharp top corners of the trench, e.g. from about 90.degree. to about 110.degree., induce stress, which is transmitted to the active regions of the substrate, resulting in degradation of the quality of the gate oxide and, hence, adversely affecting device performance and reliability. A conventional approach to this problem involves growing the oxide liner at a high enough (dry) oxidation temperature, e.g. about 950.degree. C. and above typically at 1100.degree. C., to cause the top corners of the trench to become rounded, thereby reducing the induced stress.
As feature sizes, e.g. isolation trenches, shrink to 0.25 microns and below, such as 0.18 microns, it becomes increasingly difficult to define reliable trench isolation structures. For example, the side-walls of the trench tend to expand inwardly and vertically align during edge-rounding oxidation. This condition, termed "reentrance," disadvantageously induces stress at the side-walls of the trench, which is transmitted to the active regions. With smaller feature sizes, especially in the deep submicron regime such as 0.18 microns, reentrance is exacerbated since greater aspect ratios result in greater vertical alignment of the side-walls during edge-rounding oxidation.
In addition, conducting edge-rounding oxidation at about 950.degree. C. is costly in terms of time, e.g. a period of about two to three hours, undesirably reducing production throughput. A conventional approach for improving production throughput involves raising the temperature of the edge-rounding oxidation, typically to about 1,100.degree. C., wherein sufficient edge rounding may take place in about twenty minutes. Edge-rounding oxidation at such high temperatures, however, causes other difficulties such as "slip" of the trench surface, which is the dislocation of crystal planes exposed when the trench opening is etched. Slip is a major factor of stress transmitted to the active regions, causing degradation of the gate oxide quality over the active regions, thereby adversely affecting device performance.
Attempts to enhance production throughput by other conventional means as, for example, by employing water vapor as the oxidizing species (wet oxidation) instead of molecular oxygen (dry oxidation), have generally been found to greatly aggravate the stress problems due to reentrance and slip.